After a circuit design has been synthesized, simulated, placed, and routed, designers often analyze a design for compliance with various Design For Manufacturability (DFM) requirements. In addition to DFM analysis of top-down designs, designers also analyze designs constructed from the bottom-up (where the layout is done manually polygon-by-polygon by a layout designer without use of synthesis or place-and-route tools) for compliance with DFM requirements. The DFM requirements are dependent on the particular target semiconductor process technology and are selected in an effort to increase chip yield. For example, the designer may modify the design to improve its manufacturing margin by substituting geometries with higher process margin, slightly changing the spacing and width of interconnect wires, providing fault-tolerant redundant vias, or changing the polygonal shape of some other feature of the circuit design without impacting the size or the performance of the chip (integrated circuit device).
Prior approaches have involved analyzing a design from the bottom up of a layout hierarchy. Each cell in the lowest level of the hierarchy may be analyzed to determine whether a change to the physical makeup of that cell would enhance DFM compliance. There may be many different cells in each level for which DFM requirements are to be analyzed. Furthermore, a change to a cell at one level in the layout hierarchy may create design rule violations at other levels. Finding and correcting these anomalies may be tedious, time consuming and costly.
The present invention may address one or more of the above issues.